Computer languages, whether entered in high level, assembly coding, or hexadecimal, are incomprehensible to the machine. All information is converted by the resident operating system to binary bits (1s and 0s).
All number systems, including the familiar decimal, rely on the relative position of digits to indicate their 'worth'. Each binary digit in a byte is twice the value of the bit to its right. In pure unsigned binary, the value of each binary is shown below in both decimal equivalents and powers of two:
Examples:
1000 1001 = 137
1001 1111 = 159
1111 1111 = 255
Sometimes, the following tip is useful:
A string of all 1s is 2n-1, where n=number of bits in the string.
Examples:
1111 = 24 - 1 = 15
1111 1111 1111 1111 = 216 - 1 = 65535
It is advisable, but not essential, to memorise powers of two up to the first sixteen bit positions. It is convenient to consider them divided into low-byte and high-byte as follows:
Any binary number in the high-byte position is always 256 times its low-byte value. For example, 0000 1001 would be worth 9 if low-byte, but 256*9 = 2304 if high-byte. Remember, the 6502 always stores 16-bit data in consecutive memory addresses, low-byte first.
Hex uses the 16 characters 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F to describe a nibble (4 bits):
0000=0 0001=1 0011=2 0011=3
0100=4 0101=5 0110=6 0111=7
1000=8 1001=9 1010=A 1011=B
1100=C 110l=D ll10=E ll11=F
Two hex characters describe a byte. Some examples follow:
1111 0011 = F3 0001 1011 = 1B 1100 1101 =CD 0000 0001 = 01
1111 1111 1111 1111 = FFFF 1000 1100 1010 01111 = 8CA7
Hex is based on powers of 16 so any character, depending on its position, must be multiplied by the appropriate power of 16 as follows:
163 = 4096 162 = 256 161 = 16 160 = 1
4096 | 256 | 16 | 1 | |
Using H for hex character | H | H | H | H |
Examples :
&0032=(3*16)+2=50 &00FC (15*16)+12 = 252
&00FF=(15*16)+15 = 255
&203E=(2*4096)+(3*16)+14=8254
&1111=4096+256+16+1=4369
In order to represent both positive and negative numbers in a byte, the msb (bit 7) is reserved as the 'sign' bit.
The sign bit is 1 for negative and 0 for positive numbers- For example:
0XXX XXXX is positive and 1XXX XXXX is negative.
A negative number is said to be the two's complement of the equivalent positive and vice versa. There are two ways of obtaining the two's complement of a binary number:
Examples: | Number | Two's complement |
(+7) 0000 0111 | 1111 1001 (-7) | |
(+1) 0000 0001 | 1111 1111 (-1) | |
(-2) 1111 1110 | 0000 0010 (+2) |
Method 1 can lead to errors when adding the 1, so method 2 is safer.
The two's complement of decimal numbers is found by subtracting from 256.
Example: -1 = 1-256 = 255 = 1111 1111.
The two's complement of hex numbers is found by subtracting from &FF and adding 1.
Example: -3 = &FF-3 = &FC+1 = &FD
The largest positive number in a byte is + 127 = 0111 1111 = &7F.
The largest negative number is 128 = 1000 0000 = &80.
Notes:
Decimal numbers are awkward when expressed in binary, simply because base 10 and base 2 don't mix well. BCD is a code which sacrifices efficiency for decimal compatibility. A byte is divided into two 4-bit groups (nibbles). Each nibble is coded for numbers from 0 to 9, as follows:
BCD | Decimal |
0000 | 0 |
0001 | 1 |
0010 | 2 |
0011 | 3 |
0100 | 4 |
0101 | 5 |
0110 | 6 |
0111 | 7 |
1000 | 8 |
1001 | 9 |
The six groups from 1010 to 1111, which are used for the characters A to F in hex, are illegal in BCD. A single byte can hold decimal numbers in BCD form only in the range, 0 to 99.
Examples: 0001 0011= 13 0000 01ll=07 1001 1001=99
The efficiency of a code = (number of combinations used)/total combinations).
In pure binary, all combinations are used, so the efficiency is 100%. In BCD, only 10 combinations are used out of a total of 16 possible, so the efficiency is 10/16=63% approximately. When the efficiency within a byte is calculated, the loss in information content is worse, 100/256 which is not quite 40%.
Because of the inefficiency of BCD, its use is limited. However, a large proportion of digital instrumentation delivers, or expects to receive, information in BCD form. The 6502 microprocessor obligingly processes BCD arithmetic if the D flag in the processor register is set to 1. However, it is up to the programmer to ensure that the data entering the arithmetic area is free from illegal groups.
Logic chips contain circuits which respond to, or deliver, one of two possible voltage levels. A certain family of chips (known as TTL) has set a common standard (see Fig. A.1). All members of the TTL family (there are over 300 different chips) have type numbers beginning with 74 or 74LS. The LS prefix denotes Low-power Shockty and although similar in logic function they consume less current and are faster. LS is now recommended for general use in favour of the traditional 'standard' TTL.
Logic 1 (also known as HIGH) = any voltage within the range +2.8V to 5V.
Logic 0 (also known as a LOW) = any voltage within the range 0V to +0.8V.
Fig. A.1. TTL logic levels
Any voltage in between is called a 'bad level' and will lead to indeterminate results. Bad levels are usually caused by an output over load pulling up or dragging down the voltage. Testing for HIGHs and LOWs at various points in the system can be done with a voltmeter although one of the various makes of 'logic probe' displaying either a red or green fight is more convenient and less hazardous.
A gate is essentially a logie-operated switch with one output and one or more inputs. The combination of logic voltages on the inputs determines the output state. Although the function of a gate can be described in words, a truth table with all possible input combinations is concise and unequivocal. Figure A.2 shows the six common gates in their most popular diagrammatic form, together with the corresponding truth tables. The inverter is not worth a truth table.
Notes on Fig. A.2:
Fig. A.2. The six primitive gates
Examination of the truth table reveals that it is similar to the OR but 'excludes' the bottom AND line.
Although only two inputs are shown at each gate in Fig. A.2., the TTL family include gates with as many as eight inputs. The two common chips are the 7400 quad NAND and the 7404 hex inverter. The pin connections for these appear in Fig. A.2. The power supply to the chips is marked VCC (+5V) and Gnd (0V) pin marked Vcc. Chip pin-out diagrams are always drawn looking down on to the top of the chip.
More complex chips such as decoders, buffers, counters, etc., do not always recognise a I or HIGH state as being in some way superior to a 0 or LOW state. Any input terminal which is immune to a I but activated by 0 is said to be active-LOW. Such terminals are indicated either by (a) a bar over the terminal label-such as C or clock (the bar is a Boolean symbol for negation - for example, A is the opposite state to A) or (b) a small circle or 'bubble'.
TTL logic is based on the NAND and INVERTER, the other three gates tend to be under-used and therefore not so readily available. There are three reasons for their dominance:
Traditionally, the study of logic has leant heavily on a branch of mathematics known as Boolean Algebra. It is both a useful shorthand and a powerful tool in the mathematical analysis of logic. Boolean is still useful but, for the home enthusiast, the availability of complex integrated circuits has lessened the need to design and construct systems from an assortment of gates, so time spent on studying the special algebra may not always be justified.
The main use (now) for logic gates is to 'glue' together the more complex chips which may be incompatible in some way. For instance, one chip may deliver a I where a 0 is needed, meriting an inverter in between. Another possibility is the need to enable a chip only if 'something' else is at 1. Figure A.3 shows some of the switching arrangements using gates.
Figure A.3(a) shows an AND gate simulating a series switch in the data path. A serial data stream entering can only pass through the switch if the control C is HIGH.
If a NAND gate is used, as in Fig. A.3(b), an inverter is needed. Without the inverter, the serial data stream would still pass if C is held HIGH but would be in inverted form (called the 'one's or logical complement').
Figure A.3(c) shows how it is possible to enable a chip providing both A and B inputs are held HIGH. Note that the example chip is marked CE (not chip enable) which is convenient for the LOW output from the NAND.
Fig. A.3 Uses of simple gates
Remember that the bar over the CE label is an alternative to the bubble.
The exclusive-OR gate in Fig. A.3(d) provides an easy way of controlling the phase of the output data. If the control C is held LOW, the output data stream is a replica of the input. If C is held HIGH, the output data is an inverted version of the input.
Figure A.3(c) is a simulation of a single pole, double throw switch whereby the serial data stream can be diverted to either data out I or data out 2, depending on the state of the control C. If C is held HIGH, the data emerges from the bottom gate but from the top gate if held LOW. Inverters would be needed at the outputs if NANDs were used instead of ANDs.
Logic gates deliver an output state, depending on the present input conditions. They are combinatorial devices, acting in real time and capable of analysis by simple Boolean algebra, Flip-flops are in an entirely different class because their present state depends on some event (usually a logic pulse) which occurred in the past. From this, it should be easy to conclude that flip-flops have the ability to memorise. But they can't memorise much. In fact, one flip-flop can only store a single bit so we would need eight of them to store one byte of data. A flip-flop which is storing a I is said to be set; if it is storing a 0, it is said to be reset. The four varieties of flip-flop in common use are shown in Fig. A.4.
Fig A. 4 Types of flip-flop.
The SR flip-flop. The logic symbol shows it to be a four-terminal black box. The output state is available at the 'Q' terminal which is set or reset by a negative-going pulse on S or R respectively The term negative-going means a sudden drop in voltage from HIGH to LOW. It is important to realise that, although a transition from HIGH to LOW is required, it is not necessary to maintain the LOW state. In fact, the easiest way to try it out would be momentarily to touch the S terminal with a grounded wire. !fit is already in the set state, nothing will happen. If it is in the reset state. the Q terminal will go from 0 to 1 and remain in the new state until you flick the R terminal. The action is similar to the push-on/push-off switch found on table lights it memorises the last order.
When a RS flip-flop is needed, it is customary to 'make' one from two cross-strapped NANDs (this only takes half a 7400). As a 'free gift', the Q terminal is always in the opposite state to Q. Knowledge of this can often save an inverter.
The T flip-flop. This is often called a 'toggle? because every negative-going edge of a pulse on F will change the state at Q it toggles the state backwards and forwards. The waveforms shown on Fig. A-4(b) indicate that a continuous pulse of frequency f applied to T causes an output frequency of f/2, illustrating its primary use as a frequency divide-by-two stage. The Q output will be at the same half-frequency as Q but in the opposite phase. Direct set and reset terminals, which override T, may also be present in some types.
The D flip-flop. The D stands for 'Data'. The state at Q is oblivious to the D state until a trigger pulse arrives at T. When the negative going edge of the trigger arrives, the state of D (at that time) is passed (latched) into the flip-flop. In other words, the Q state is always the state which D was, prior to the arrival of the trigger. The 7475 is a quad D-type latch, containing four identical D flip-flops. Two of these can be used to latch in a byte of data.
The JK flip-flop. This is a versatile breed of flip-flop, shown in Fig. A.4(d). The logic state on the J,K terminals decide the eventual state of Q after the next trigger pulse on T. The action is best described with the aid of the following truth table:
J | K | State of Q after next trigger |
0 | 0 | No change |
0 | 1 | Reset (Q=0) |
1 | 0 | Set (Q=0) |
1 | 1 | Change |
Note that when J and K are both 0, the flip-flop is paralysed, unable to respond to any triggers.
If J and K are both held at 1, a trigger will always change the state. In other words, this perm of J, K transforms it to a T flip-flop.
If J is joined to K by an inverter, it is transformed to a D flip-flop, the J terminal acting as a D.
From this, it is easy to see why the JK flip-flop was described as versatile.
Finally, it should be mentioned that some diagrams will choose different labels for the trigger terminal. The terminal we have marked T may, in some diagrams, be marked clock or just C.
A microprocessor system is based on the common bus. The output data from RAM, ROM, etc., are all wired in parallel across the same wires. It is important that such devices in the disabled state are effectively disconnected from the common bus. Normal TTL logic allows inputs to be connected together but under no circumstances must outputs be connected together unless they are of the class known as open-collector. Figure A.5(a) shows the idea behind wired-OR connections.
Fig. A.5. Wired-OR and tristate
The output stage of normal TTL consists of two transistors in series across the 5 V supply (known as totem pole) with the gate output emerging from the centre point. The top transistor is missing in open-collector types and the feed to the 5 V fine must come from an external pull-up resistor. This allows several outputs to be connected together, providing they all share the same pull-up resistor. Many of the popular chips in the TTL family are available in both standard and open-collector version.
Although wired-OR connections are useful in odd places, the solution is too messy for computer bus work. The alternative, and cleaner, solution is to provide chips with tristate outputs as shown in Fig. A.5(b). An extra transistor is built in to each output line, acting as a series switch and turned on or off by the enable terminal. When the chip is disabled, the outputs are effectively removed from the bus. The TTL chips offering tristate outputs are normally more complex than simple gates. RAM and ROM chips are almost always tristate.
Some disconcerting effects can occur if logic voltages are applied by means of an ordinary mechanical switch, particularly if the terminal supplied expects a single pulse. Due to the natural resonance of the operating spring, switches bounce backwards and forwards several times before coming to rest in the final position. The evil is called switch-bounce and can be overcome by either of the following two methods:
Fig. A.6. Switch de-bounce circuit
Small lamps are popular for displaying logic states. All lamps take current which can be ill afforded in logic work. Incandescent filament lamps are sluggish and take 50 mA or more. Neons take negligible current but require about 80 volts before they emit the characteristic red glow. This leaves the light-emitting diode (LED) as the only serious contender. They give a reasonable light with about 5mA and only drop about 1.2 volts. They must always be fed via a series resistor somewhere in the chain in order to ensure current, rather than voltage, drive. They are best driven from the output of an inverter as shown in Fig. A.7.
Fig. A.7. Feeding a LED.
The LED lights when a 1 is applied to the inverter input. The inverter output then drops to near ground, completing the circuit through the LED. The output of the inverter is said to be sinking the LED current to ground.
Devices which require current in excess of 20 mA or voltages in excess of 5V cannot be driven from logic circuits without help. This help can be supplied by the familiar electromagnetic relay, the opto-isolator or a combination of both. Figure A£ shows some arrangements.
In spite of the glamour associated with the semiconductor age, there are still uses for the traditional electromagnetic relay. Design methods have improved and the modern forms are efficient, physically small and take relatively low currents. Although no different in principle, the variant known as the reed relay, shown in Fig. A.8(c), is common-place in modern interface circuitry. The operating contacts are enclosed within a glass tube filled with inert gas, which prevents the build-up of oxidation products. Because of this, the contact fife is much higher than in the traditional open-contact relay. The operating coil is a separate component slipped over the tube and therefore can cater for a variety of current and impedance requirements.
Relays fulfil two primary requirements of the power interface:
Fig. A.8. Relays and opto-isolator drives.
They must never be used without a reverse diode across the operating coil. The diode safeguards the logic circuits from induced voltages which appear when the current is interrupted. Figure A.8(b) shows a typical drive arrangement, using a common npn transistor as a current amplifier. The transistor conducts through the operating coil of the relay. The 1K resistor supplying the requisite base current The presence of the inverter gate means that the transistor conducts on a logic 0 input and switches off on a logic I. This is a case of an active-low drive causing a back-to-front action. If this is undesirable, the remedy is to insert an extra series inverter to bring it right again or substitute a non-inverting buffer gate. In either case, some form of logic gate is desirable in home constructed projects rather than a direct raw feed from the computer output port. Gates are cheap, computers aren't!
The opto-isolator is another popular component in interface work. Like the electromagnetic relay, the objective is to isolate electrically the computer from any high power {voltage} current components. In fact, the only connection is via the light emitted from a small LED falling on the base of a light-sensitive transistor. They are available singly as 6-pin chips, with the diode and transistor buried within the silicon. A typical circuit using a single opto-isolator is shown in Fig. A.8(a). The RS 305759 is only one of the many types available in the catalogues.
The box marked 'load' is a blanket term covering any contraption driven by the isolator. In all probability, this will include yet another transistor because the opto-isolator introduces a power 'gain.' of less than unity (typically 0.2). To convert the loss into a gain, some opto-isolators incorporate two transistors and are classified as Darlington-connected. Some chips are available which contain four independent opto-isolators so two of these could handle the output from an 8-bit port.
When the logic state changes from 0 to 1, or vice versa, logic chips expect the change to be rapid. In other words, the wave form should display, as far as possible, straight-sided pulses. If the input changes are sluggish, the behaviour could be impaired, particularly for clock-type inputs . If the input is obtained from the output of another logic circuit and the wiring between the two is not too long, there is no problem. However, if the input is obtained from an analogue, or 'home-made' source, the waveform is probably suspect and must be cleaned up before qualifying as a legitimate gate input. The 74 logic series has the answer in the form of the schmitt trigger, a standard circuit which accepts a poor pulse shape and transforms it into a steep-sided version. Figure A9 shows the gate symbol with typical input and output waveforms. The 7414 is a hex schmitt inverter, performing in the same way as a normal inverter but accepts poor waveforms. The schmtt does not protect against voltages which are out of range. It offers waveform but not voltage protection.
Fig. A.9. The schmitt trigger.
With reference to the mention of 'long' wires, it is worth pointing out that distributed capacity across wires, or between wires and ground, is often a cause of weird faults. it is sometimes a source of complaint that manufacturers of peripheral equipment appear to be miserly in the length of connecting cable supplied. In all fairness, this is not always due to cost penny-pinching. It is simply a wise precaution to avoid complaints of erratic behaviour which might arise if the cable length were increased. Apart from distributed capacity, the longer the wire, the more chance of picking up stray induced voltages.
It must be admitted that discussion of these chips is a little out of place here. The 555 timer chip is not strictly a logic circuit although, if operated from a +5V supply, it accepts and delivers reasonable TTL voltage states. It is versatile, very low-priced, and easy to use. We are concerned here only with its use as a hardware timer. That is to say, a device which, on receipt of a single narrow pulse, delivers an output HIGH state for a certain time before reverting to the quiescent LOW state automatically. Figure A10 (a) shows the pin connections, wiring and waveforms.
Fig. A.10. The 555 ZN1034E timers.
The 555 is ideal for cases where a single pulse from the computer can turn on a device (electric motor, perhaps) but is not required to stop under computer control. It is realised, of course, that the BBC machine includes programmable timer facilities so the job could have been entirely software-controlled without a 555. However, it is good to be aware of alternative possibilities.
The output pulse-width, which determines the ON .time of the device, is dependent on the value of C and R according to the following formula:
T = 1.1 CR (where C is in pF and R is in megohms)
For example, if C= 0. I mF and R 100K, the ON time will be 0.011 seconds. The figures illustrate that the 555 is not generally suitable for long time periods. It is not recommended to use R values greater than I M, and capacities of the order of some microfarads means using electrolytics with wide tolerances. For periods over several seconds up to minutes, it is better to use one of the more sophisticated timers such as the ZN1034E shown in Fig. A.10(b). The timing formula is:
T = 2736 CR (where C is in mF and R in megohms)
The multiplication factor 2736 is achieved by an internal l2-bit binary counter allowing time periods up to an hour or more. A us-gful feature is the provision of two complementary outputs, marked Q and Q in the diagram. It is a complex l4-pin chip with some of the pins allocated to external calibration resistors but only the simplified wiring is shown. To utilise the full potential, it is worth sending for detailed data sheets.
A decoder will have several outputs but only one selected output can be activated at a time. The particular output depends on the specific combination applied to the selection input. Three select terminals can provide only eight different combinations of binary digits, the rule being:
Number of combinations of n bits = 2n
For example, to select any one of sixteen outputs requires four select inputs. There is a wide range of decoders in the TTL series. In addition to the select inputs, there will be one or more enabling inputs, allowing decoders to be linked together. Some of these may be active-high and some active-low. It is important to realise that all enable inputs must be activated before the chip becomes 'live'.
A demultiplexer routes serial input data to one particular output line and is the logic equivalent to a single pole multi way switch. Like the decoder, the particular output selected depends on the combination supplied to the select terminals. In fact, a decoder with enable inputs can be used as a demultiplexer by feeding the data to one which is active-high.
These are mirror images of demultiplexers. They route any one of many input data sources to a single output line. The particular input source depends on the combination applied to the select inputs. The usual enable terminals will be present in most TTL chips.
An encoder delivers a particular binary pattern on the output terminals. depending on which of the many input lines is activated. For example, there could be ten inputs, each capable of producing a unique four-bit pattern on the outputs and acting as a decimal to binary encoder. Most microcomputer keyboards are decoded by scanning software but some of the more expensive types are hardware encoded.
A counter is essentially a device which delivers an output binary pattern which changes on receipt of each input pulse. The TTL range offers a wide variety of counters. They may be classified as follows:
Binary counters. The input pulses cause the four-bit output to progress from 0000 to 1111 in a simple binary sequence. The pulse starts the count again at 0000.
BCD counters. The input pulses cause the four-bit output to progress from 0000 to 1001 (0 to 9 decimal). The tenth pulse starts the count again at 0000.
All counters will be supplied with a reset-to-zero input and most supply a terminal which emits a pulse when the count goes over the top to 0000. This is useful for cascading the output of one counter to the input of another. Two binary counters in cascade would then handle counts up to 11111111 (255 decimal) and two BCD counters up to 1001 1001 (99 decimal). There is another classification according to the direction of count. For example, those described above are up-counters but some varieties can be persuaded to down-count. For example, a four-bit binary down-counter has 1111 as the 'reset' state and decreases on each input pulse towards 0D00. Downcounters are not supplied as such but some of the more sophisticated varieties have a control terminal which can be maintained HIGH for upcount and LOW for down-count. It is worth mentioning that an ordinary up-counter can be turned into a down-counter by inverting the outputs.
It is self-evident that a shift-register shifts but, as with counters, there are generic variants depending on the direction of shift (left or right) and whether the initialised data is applied serially or in parallel. They will ail Binary and Logic 233 have a 'shift' terminal (marked T or Clock). Every pulse on T shifts the contents one place, bits being pushed out at one end.
Parallel-in-parallel-outs, known as PIPOs, accept parallel data on the four inputs, and data is available on the four output lines after the shift pulses have ended. The new input data is only let in to the register when an enabling level is applied to the appropriate terminal.
Parallel-in-serial-outs, known as PISOs, are similar to above But the output data can only be obtained a bit at a time on the serial output line.
Whatever other facilities they posses, shift-registers will always have serial-in and serial-out terminals. Many varieties exist in the TTL range. Some handle St-bits and some can shift left or right depending on the state of a control terminal. The most obvious use for shift-registers is for parallel to serial or serial to parallel conversion.
A buffer is a temporary holding register for data, the contents of which are subject to a latching pulse. Typically, there will be four data inputs, four data outputs and a terminal which is used to latch in the new data. Data variations at the input are 'unseen' until a latching pulse is applied when the current data overwrites the old. Some buffers have tristate outputs and are bi-directional.