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Chapter One
Architecture of the BBC Machine

Background material

Although not strictly essential, the would-be machine code programmer will find it helpful to take some interest in the hardware layout of the computer and the historical events which led up to the present design. Such interest need not extend to detailed electronics because it is possible to gain a fair understanding of the overall system without it.
The hardware of any microcomputer can be described as a collection of integrated circuits (chips) and a few separate (discrete) components such as resistors, capacitors and transistors stuck on a printed circuit board (the pcb). Communication with the outside world (peripherals) is via an assortment of plugs or sockets accessible from the back. Some computers may have more memory than others, may have more plugs and sockets and perhaps a few more chips than others but it would be difficult to pinpoint any profound differences in the hardware design.

von Neumann's influence

A computer, whether it is one of the mainframe giants or a small one designed for home use, will in all probability be a 'von Neumann machine' (discussed in Chapter 3). That is to say, it will be designed in accordance with fundamental principles laid down by the eminent mathematician of that name. Although it has always been fashionable to credit Charles Babbage with the 'discovery' of the computer, it is questionable whether his contraption of cogwheels and levers had any real effect on the evolution of the modern computer. It was left to von Neumann to set out the first 'block schematic', suggest the main data flow paths and the timing sequences required to build a practical automatic digital computer. Because of his contribution to computer science, John von Neumann (1903-1957) is affectionately known in many quarters as the 'father of the computer' although, like all leaders of a team, he probably received a disproportionate share of the credit.
It is sad that all great men eventually have their greatness disputed. In recent years, poor old von Neumann, or rather his principle, has been attacked. It is said by some that computing progress has been stifled by slavish adherence to his original concepts of sequential data flow. They argue that in spite of the enormous improvements in computer power which have taken place over the last four decades, these have been due mainly to improvements in computing components rather than developments in computing science. To some extent, this is true. In the case of internal memory, for instance, there is no fundamental difference between the old magnetic core memory with its thousands of ferrite rings wire- knitted together and the modern semiconductor RAM chip. Similar comparisons can be made between the central processor of the earlier machines and the modern variety. The valves gave way to discrete transistors which in turn gave way to boards full of logic chips. Eventually, the central processor, particularly in the case of the minicomputer and microcomputer, became available as the single-chip 'microprocessor'. In spite of all this it would be true to say that apart from enormous reductions in cost and size, most modern computers are not profoundly different in principle to their World War II ancestors; they are still van Neumann machines.

The computer generations

Some attempt has been made to classify computers into so-called 'generations'. The early machines which used valves belonged to the First Generation, those which used discrete transistors became the Second Generation. When integrated circuits replaced discretes the Third Generation was born (in the mid-sixties). The first integrated circuits contained between four to ten simple logic gates per chip which, at the time, was heralded as an exciting breakthrough in technology. The most famous chip in that era was the 7400 quad NAND gate, manufactured by Texas Instruments, and one of a family of chips known as the 'TTL logic series'. It is still going strong at the time of writing. Before the marvel of TTL had time to be digested, Silicon Valley in California produced its next bombshell 'Large Scale Integration' or LSI which earned the name of the Fourth Generation. LSI chips were first produced as semiconductor read/write memories. They were in fact 'dynamic RAMs' and were directly responsible for the virtual death of the traditional core memory.

The micro processor

In 1971, Intel launched the first microprocessor which, quite unexpectedly, changed the entire nature of computing. It was unexpected in the sense that the device was never intended to be used in any other way than as a control element in digital-operated machinery. Instead, the 4004 sparked off a full scale development spree as engineers began to appreciate the enormous potential of such a device. Silicon Valley became split into fragments, with new firms each rushing to improve on the success of the 4004. The first improvement was Intel's 8080, closely followed by Motorola's 6800 and the Zilog Z80. The microprocessor used in the BBC machine is the 6502 which, as we shall see later, may be considered as a modified 6800. Apart from the original 4004, which was a four-bit microprocessor, the others mentioned above are eight bits wide or, to use technical language, they have a 'word length' of eight-bits. This means that all data transfers into or out of the microprocessor take place in bunches of eight binary bits. In relation to the more traditional computers, a word length of eight bits is embarrassingly small and places a heavy responsibility on the designer of the software operating system. It is complicated process to handle data efficiently, particularly when the data is in the form of large mumbers greater than 255 decimal. The only way it can be done is to handle numbers by eight-bit instalments which is time-consuming and therefore reduces computing power.

16-bit microprocessors

Over the last few years, a number of 16-bit microprocessors have appeared on the market although they have yet to enjoy the low prices resulting from mass marketing. Owners of the BBC machine will be aware of the Second Processor options, one of which is boasting the presence of a 16-bit microprocessor, the 16032. Not only is the 16032 a true 16-bit chip, some of the internal registers can handle 32 bits at a time. The resulting power of the BBC machine will then be equivalent to a minicomputer, rather than a microcomputer. When considering the cost of the 16-bit second processor (which admittedly is rather high) it should be remembered that the computing power available will be out of this world at least the microcomputing world. Those who are considering the purchase of the Second Processor option would be advised to think carefully before buying the 'cheaper' B-bit versions. They will be using either another 6502 or a Z80. Of course, there will be a great improvement, apart from the extra 64 K of memory but the improvement will not be revolutionary. The I6-bit version will cost more than twice as much but will elevate the system to an entirely new dimension. From the viewpoint of the machine code programmer, the advantages will be even more apparent. It is dangerous to prophesy future market tendencies but it is quite probable that there will be an astonishing demand for the 16-bit processor. In fact, it may be a case of history repeating itself. The original miscalculation was the false estimate of the relative popularities of the Model A and the Mode! B. In spite of the £100 extra in price, the demand for the Model B was much higher than for the Model A, and was one of the factors which contributed to the chaos during the launching year of the BBC system.

Software development

Improvements in software have not kept pace with hardware improvements. It is unlikely that they ever will. Machines are being built with frightening power and it is becoming increasingly difficult to produce software of sufficient complexity to exploit fully the hardware available. The computing world is currently obsessed with the new breed of computers being designed, alleged to have built-in intelligence. These will represent the Fifth Generation. Already we are subjected to a new crop of buzzwords relating to 'artificial intelligence' or AI. Whether or not it is sensible to credit a computer (even a fifth generation species) with intelligence before even humans have agreed on a definition of their own intelligence is questionable. In any case, what is exactly meant by 'artificial'? Perhaps we shall soon have artificial plastic!

Hardware of the BBC Micro

Although the User Guide and the advertisement brochures fist ail the various input} output facilities available, it will do no harm to repeat some of it here with some extra details aimed at the machine code programmer. When programming in BASIC, or indeed any high level language, it is not necessary, perhaps not even advisable, to worry much about the mysteries under the bonnet. In the case of machine code programming you cannot afford to be totally ignorant of the machine itself. Although the resident assembler provides some protection from the harsh realities of life beneath the keyboard it is still very much a game of battling directly with a primitive machine.

Removing the top cover

Even if you have no experience with electronic equipment you should not hesitate to remove the top cover of the machine and have a good look at what lies beneath. It is an easy task if carried out as follows, although it should be pointed out that technically the guarantee would be invalidated so be very careful!

  1. Switch off at the wall and remove the three-pin plug from the socket.
  2. Wait for half a minute to allow stored charges to decay.
  3. Locate the two fixing screws at the back of the case (probably marked FIX) and remove them.
  4. Locate the two fixing screws underneath the case at the front, beneath the keyboard (probably marked FIX), and remove them.
  5. Carefully lift away the top case, exposing the circuit board beneath.

When ready to replace the cover again, take care that you don't bend or damage the three tiny red fights at the left of the space-bar. They are supported only by their own connecting wires and it is easy to trap them beneath the cover.

Locating the components

The dominant sight, when first exposing the interior, is the shiny aluminium (or perhaps steel) box which occupies a large area at the left. This is the 'power pack' which converts the dangerously high (230-240 volts) mains supply into low voltages supplying power to the various components on the circuit board. The supplies are +5V at 3.75 A, -5V at 0.lA, +12V at l.25A. All these voltages are with respect to ground (zero volts). Such low voltages are not dangerous so all areas of the board outside the metal cased power pack offer no electric shock hazards to the human finger. In spite of this, it is unwise to poke around too much because your fingers could cause damage to some of the delicate components on the board. Some of the chips, particularly the large ones, are very susceptible to static charges which can accumulate on the fingers although, theoretically, they are immune once they are secured in the circuit board.
At the top right-hand corner is a small metal box marked with the manufacturer's trade mark ASTEC. This is the UHF modulator which, if you are relying on a TV as the screen output device, modulates the logic voltages from the board onto an ultra high frequency signal, which is interpreted by the TV as a bona fide aerial signal. The output is via a coaxial cable outlet at the back marked UHF OUT, If you are using a purpose-built monitor rather than a TV, there are two alternative outputs. One of these is a 'composite video' marked VIDEO OUT and is intended to accommodate some makes of black and white monitors. The interface components include one of the few discrete transistors used. According to the circuit details on page 504 of the User Guide it appears impossible to obtain colour output unless a small modification is made. The remaining screen output is the RGE (Red Green Blue) interface and is the most efficient method of energising a colour monitor, providing a direct and uncluttered signal. The Microvitec colour monitor would use the RGB output

Sending characters to screen output

As far as machine code programming is concerned, irrespective of the particular output in use, characters can be sent direct to a screen address by use of an STA instruction or, preferably, by OSWRCH. It is appreciated that these code words will have little meaning to those who are entirely new to machine code. ST A in machine code is similar to POKE and OSWRCH is a resident operating system subroutine, standing for Operating System WRite CHaracter. Our reason for prematurely introducing these machine code terms is to emphasise a golden guideline of the BBC machine:

Always use the official operating system subroutines to send or receive data to peripherals

This means avoiding absolute addressing of peripherals (no poking). Note carefully that this is a guideline and not a rule. The reason behind it is tied up with the second processor - should you ever buy one. Any software you write using absolute and addressing of peripherals may not work when the second processor is connected. It should be mentioned that direct access to screen addresses will produce faster responses than using OSWRCH.

The ROM chips

Once the top case has been removed, as previously described, the keyboard can be lifted off by undoing the two exposed nuts. If the removal is merely to examine the components beneath, it is not essential to unplug the keyboard. In fact it is unwise to plug and unplug any microcomputer connections more frequently than necessary. Beneath the keyboard to the right and near the bottom are five sockets for ROM chips. Except for the few thousand early models, only two of these sockets will be inhabited. The socket at the extreme left houses a I6-pin ROM which is the BASIC language interpreter. Next to this is the Operating System ROM. You should ensure that this ROM is the 'latest Series I' model because some of the earlier types had a slightly suspect operating system called 'Version 0.1'. It is easy to find out which operating system you have by entering *HELP followed by RETURN. The response should be:

OS 1.20

A response such as OS 0.1 indicates that the old ROM is resident.

Bank-switching

The remaining three sockets are left blank for additional ROMs. There are many firms which supply special ROMs which can be plugged into the vacant sockets: for example, Acorn's word processor called 'View' or the other popular word processor„ called 'Wordwise' marketed by Computer Concepts. There are also several language ROMs available and many application ROMs. The total direct addressing space available on the 6502 microprocessor is 64K. The operating system takes 16K, the BASIC language ROM occupies another 16K and the remaining 32 K on the Model B machine is devoted to RAM. This means there is no direct addressing space left for any additional ROMs. The method employed to escape from the impasse is a technique known as bank-switching. This allows the resident BASIC language ROM to be 'switched out' and replaced by one of the special ROMs. Thus it is an 'A or B but not both' situation. Bank-switching is software-controlled which normally defaults to BASIC under power-up conditions. However, if additional ROMs are in place, the operating system will be aware of it (or them) and the new default condition on power-up is to the ROM in the right-most position. For example, if Wordwise is plugged into any one of the vacant sockets, the default condition on power-up will be Wordwise instead of BASIC. To switch over to BASIC it will be necessary to enter* BASIC or the abbreviated form *B.

The response to the BASIC command *HELP will now be modified as foliows:

WORDWISE

OS 1.20

The response indicates that Wordwise has priority over BASIC on power-up because it is displayed first. If the relative priorities are found in practice to be irksome the situation can easily be changed by swopping over the two ROMs so that the BASIC ROM is right-most. The unprecedented popularity of the BBC machine has stimulated professional programmers with the result that many other high-level languages are available in ROM form including PASCAL, FORTH and LISP.

PROM programmers

An alternative use for the spare sockets is to enable you to insert your own EPROMs. They can be bought in blank form; that is to say, they have no programs 'firmed' in. With the aid of special kits called EPROM programmers, it is possible to transfer a machine code program from RAM to the EPROM which can then be plugged into one of the spare sockets. There is one small snag, however. Make sure that all bugs are removed before you transfer it to EPROM because you cannot change parts of the program. It is anal! or nothing process. If there is a bug in the EPROM, it is necessary to erase the entire contents and start again. The erasure process requires the chip to be exposed for a certain time in a special box containing an ultra-violet lamp. A fully erased EPROM contains '1's in every bit position so all the addressed locations contain FF (hex). A discussion on hex notation appears in Chapter 3.

The user port

The BBC machine has standard interfaces for printers, disk, cassette etc. and also caters for individual needs by means of the user port. This is a multipin socket outlet accessible from the underside of the case. It is completely undedicated and is therefore free to activate any device you choose - providing you know how to make the correct connections and are able to write suitable software.
Although the port behaves as an independent set of outlets, it is actually one half of a complex input} output chip called a Versatile Interface Adaptor (VIA for short) bearing the type number 6522. The two halves of the VIA are referred to as the 'A' and 'B' sides. The B side is dedicated to the parallel printer interface and the A side is the user port. The port is essentially a ten-wire interface between the computer and the world outside. Eight of the wires are used for data and two for controlling the data. Any one of the data wires can be programmed to behave as either an input or an output, which obviously adds to the versatility. It is worth examining some of the possibilities:

  1. Assuming a device could be switched ON or OFF by simple logic, we could independently control eight of them. They would all be programmed initially as outputs.
  2. Any one of eight devices could send a logic signal back to the computer.
  3. They would all require initial programming as inputs.
  4. Three devices could be controlled by the computer and five could send signals back.
  5. By employing simple decoding chips, it would be possible to control any one of 256 output devices. Conversely, any one of 256 devices could send a signal to the computer.
  6. Two devices each requiring four inputs could be driven in parallel.

With regard to the two control wires mentioned above, one is always an input but the other can be programmed as an input or output. The input control wire can be used to initiate an interrupt sequence. That is to say, an input signal can cause the present program to be interrupted and a jump made to an entirely different program. (Interrupts are discussed in Chapter 2,) The use of interrupts can be a hazardous exercise because the entire operating system is already controlled by interrupts. For example, when the computer is switched on and a flashing cursor is displayed, the machine appears docile and in a resting state. This is far from true. In fact there is a furious battle going on in the operating system. Every few milliseconds, the display system rudely interrupts whatever is going on (most probably waiting for a key to be pressed) to repaint the screen picture. The screen display only appears stationary to the eye because every single dot, which makes up the 'picture', is repainted many times per second. Due to the persistence of normal vision, a screen picture need only be repainted every few milliseconds so there is ample time in between for the computer to carry out your orders in a series of interrupted instalments.

Interrupt requests

If the order involves the use of a peripheral, such as a cassette tape recorder or a printer, it is probable that the operating system will handle them by yet another interrupt sequence. The question of relative priorities then arises. For example, what should happen if the printer sends a signal to interrupt while the system is already in an interrupt condition, such as repainting the screen?
In real life, the needs of certain people have priority claims over the needs of others in order to maintain a well-ordered, stable society. A similar arrangement has been found to work well in computing systems. Certain interrupts must be considered to have higher precedence than others and permission to interrupt must be granted first rather than allowing a disorganised free-for-all. The 6502 microprocessor is fitted with interrupt request logic which, in conjunction with appropriate software, can maintain tranquillity. When an interrupt request signal from a peripheral appears on a control input line, it is passed, via the VIA, to the microprocessor. A certain bit in the processor (called the 'interrupt mask bit') is examined. If the mask bit is a '0', the interrupt is allowed. If, however, the bit is in the '1' state the request is noted but activation is delayed until such time as the mask bit is reset to zero. The actual setting or resetting of the mask bit is, of course, the responsibility of the programmer. We shall see later that the 6502 microprocessor has two instructions for defining the state of the mask bit. To set the mask to '1', the instruction is SEI (SEt I bit). To reset the mask to '0', the instruction is CLI (CLear I bit). The mask is referred to as the 'I bit' in 6502 language.

Serial and parallel interfaces

Most computers, including the BBC model, use the ASCII code to represent characters. Each character requires one byte (a byte is eight binary bits). There are two ways of sending these characters along wires to, say, a printer some distance away:

  1. Parallel transmission, in which eight wires are used to send every bit of the code simultaneously.
  2. Serial transmission, in which the eight bits are sent, one behind the other, along a single wire.

It is worth examining the relative merits of the two systems because the BBC machine provides provisions for both serial and parallel feeding of peripherals. Superficially, it would appear that parallel transmission would be much faster, eight times faster than serial. This is true but in most cases, particularly where printers are concerned, the difference is seldom of any interest because the weakest link in the chain is the printer rather than the transmission delay along the wires. Thus, if we run the same printer by serial transmission and then change to parallel (assuming the printer allows either option) we will find no difference in printing speed. The cogs and levers still take up more than 99% of the printing time. Traditionally, serial transmission dominated the scene, particularly for feeding the now almost obsolete Teletype, a two-way device which combined a sending keyboard, a paper tape reader/punch and a printer. It was Centronics, a company which specialises in printers, which contributed to the popularity of the parallel transmission. In fact, their design for allocating the various control functions has been copied and virtually standardised by what is known as the Centronics interface. The BBC has a parallel Centronics interface although it is simply labelled above the socket as the 'Printer'.

The RS423 interface

The BBC Micro also has provisions for a serial interface via the socket labelled 'RS423' which now deserves some explanation. As stated above, the Teletype was the standard peripheral in earlier days and the serial interface was known as the '20mA current loop' because it demanded a current of 20 milliamps from the computer to drive the printer relays. This was in the days when computers were massive things and 20 milliamps was a negligible drain on the relatively enormous power supplies of the time. When logic chips arrived on the scene, operating on almost negligible current, 20 milliamps just to drive the printer started to become almost absurd. One of the results was the formation of a new serial 'standard' called the RS232 interface which demanded only a small current drive. In fact it would be better to consider it as a voltage rather than a current driven system. The RS423 interface is almost identical (in fact compatible) with the RS232 but in many respects it is superior. There is always an upper limit on the length of wires between the sending and receiving end of a serial transmission line. The RS423 allows a longer length than the RS232.
Although the printer has featured in the above discussion on the RS423, it is a general purpose interrupt driven interface, capable of linking any device which requires a serial interface. For example, it can be used to connect two BBC machines together so they can mutually converse with each other. Figure 1.1 shows the interconnections required between the two sockets. In addition to the wiring shown, small software routine is necessary before the two machines can talk to each other.

Fig. 1.1. Connecting two BBC machines together

The serial nature of RS423 data requires some rather complex logic operations. One difficulty, inherent in all serial transmissions, is the method of establishing some form of marker signal to indicate the three distinct parts of the message - for example, the quiescent state in between characters, the start of a character and its end. This is handled by the 'start' and 'stop' bits at either end of the 8-bit character string. For some time now, manufacturers of microprocessors have always supplied ready-made solutions to such problems in the shape of specialised chips. The common name for the class of chip which handles the serial transmission of data is 'Asynchronous Serial Interface Adaptor' (ASIA for short). The particular species in the BBC machine is the 6850. This chip converts the g-bit parallel output from the computer data bus into serial form. It also generates the start and stop bits, together with the correct timing circuitry. The 6850 is to serial interfacing as the 6522 is to parallel; that is to say, the ASIA and the VIA are serial and parallel interfaces respectively.

Analogue to digital conversion

Digital computers are designed to operate in a restricted, but nevertheless predictable, two-state environment Voltages are either in the '1' state (about +5 volts) or in the '0' state (about 0 volts). Conditions in the world outside have no such restrictions. Physical variables, such as wind, temperature, pressure, electrical voltages etc., can assume a wide range of values. A voltage which somehow is made proportional to a particular physical quantity is called a voltage analogue of that quantity. Thus, if a wind velocity over the range 0 to 100 miles per hour were represented by a voltage between 0 and 10, the scaling factor would be 10 miles per volt. The particular gadget which converted the wind speed to voltage would be termed a transducer and, in its most simple form, could be an electrical generator with the shaft driven by wind blades. Linearity of the scale would obviously depend on a strictly proportional relationship between shaft speed and output voltage. However, a program could easily be written to account for non-linearity in any transducer.
The BBC machine has a special analogue to digital input socket marked 'Analogue In'. It enables any one of four analogue input channels to be converted to a digital number. Unfortunately, this facility, if some of the popular computing magazines are to be believed, appears to be used almost entirely for waggling games paddles. This is a pity because the interface is suitable for a wide range of applications. Figure 1.2 shows how to wire up a simple circuit in order to experiment with the converter.
The top diagram, Fig. 1.2(a), shows the connections between a 10K potentiometer (known in electronic circles as a 'pot') and the 15-pin Analogue-In socket at the rear of the machine. It enables any voltage between 0 volts and a nominal 1.8 volts to be applied to the analogue-to-digital input by twiddling the knob on the pot. A word of warning is not out of place here. The wiring from the pot should never be soldered directly to the pins on the computer socket. Always use a plug and socket connection. There are many firms that supply the correct socket already attached to a ribbon cable. Soldering direct to the machine's Analogue-In socket is crude and unprofessional. In fact this warning applies to all external connections because there is always a danger of the leads shorting together by wisps of solder. The output from the pot is connected to pin 15 which is Channel 0 although there is no reason why any of the other three possible channels could not be used.

Fig. 1.2. Analogue to digital hook-up.

Figure 1.2(b) is for the benefit of those who feel happier if they know what they are doing. The circuitry to the left of the dotted line is within the computer. The 1.8 voltage reference line is obtained internally from a divider chain across the +5 volt supply to ground. The three silicon diodes are in series with each other, providing a total forward voltage drop of about 1.8 volts. Silicon diodes have the useful property of dropping about 0.6 volts when in forward conduction and within reason, irrespective of the current through them. However, it would be unreasonable to expect exactly 1.8 volts output to the pot.
The wiring can be tested out with a simple few lines in BASIC as described under the keyword ADVAL on pages 202-204 in the User Guide. (Machine code versions appear later.)

Using the four channels

The chip performing the analogue conversion to digital is an interrupt-driven D7002: a standard, but nevertheless sophisticated, component. It converts the analogue input voltage into a 12-bit binary number so each additional bit increases the number by an increment of 1/4096. It allows any one of four input voltage channels to be measured. Figure 1.3 shows how to experiment with four controlling pots.

Fig. 1.3. Four-channel control.

The four pots are in parallel across the reference supply (pin 11 and 5) with sliders connected to the channel input, pins 15, 7, 12 and 4. If 10K pots are used, the total load of 2.5K is a little on the heavy side. The current limiting resistance, R71, shown previously in Fig. 1.2, causes the voltage to the stabilising diodes to be pulled down to a rather low value of 2.5 volts. The next highest preferred value of pot would be a reasonable compromise. The four controls can be tested immediately by the following simple BASIC lines:

10 MODE 7:Channe1=1

20 REPEAT

30 Analogue=ADVAL(Channel)

40 PRINTTTAB(5,10+Channe1)"Channel nu

mber ";Channel,Analogue

50 K=INKEY(100)

60 Channel =Channel +1

70 IF Channel>4 THEN Channel=1

80 UNTIL 2=3

The program will continuously display all four channel readings in the form of 5-digit decimal numbers, the readings changing as the pots are varied. Line 50 is to slow up the changes to prevent blurring. It is interesting to try out the above even if you have not wired anything to the Analogue-in socket. The display will show four numbers, varying in the region of 50000. The reason for this is the open-circuit condition of the input channels causing an indeterminate 'floating-to-high' state. As the User Guide explains (page 202), the internal operating system has allowed for possible replacement of the D7002 by a higher resolution version, so the digitised range appears as 0 to 65520 instead of 0 to 4095. As a result, the readings go up in increments of 16 rather than 1.

Floppy disk controller

Floppy disks pose a greater interfacing problem to both the hardware and software engineer than the relatively simple cassette tape backing store. A special disk controller chip, the 827 I, is responsible for the primary hardware interface. The repertoire of extra commands required to make full use of the disk filing system is buried in a special ROM, known as the DOS (Disk Operating System) or the DFS (Disk Filing System). The necessary power to drive the disk motor and the disk electronics is supplied from a 40-pin socket beneath the keyboard.

Memory mapping and page numbers

The peripheral devices so far discussed are standard to the model B, with the exception of the disk interface components which are optional extras. All peripherals are memory-mapped, meaning they are all accessed as if they were normal memory locations rather than responding to special machine code instructions. Thus, the floppy disk controller chip 'resides' at the five memory locations &FE80, &FE81, &FE82, &FE83 and &FE84. The '&' prefix indicates that the numbers are in hexadecimal rather than decimal. The hexadecimal (hex for short) counting system is widely used in machine code work, particularly when referring to machine addresses. If hex is unfamiliar to you, see page 71 of the User Guide or skip to Appendix A of this book. A complete hexadecimal address consists of four hex digits. The first two digits are best thought of as the page number and the second two digits as the position on the page. Referring back to the five addresses occupied by the floppy disk controller, we could say they are all on page &FE of the memory map.

Sheila addresses

The machine addresses for all the peripheral interface chips so far discussed are on page &FE. This particular page has been given the rather charming name of Sheila. Thus the Sheila address band is between &FE00 to &FEFF. The positions on the page are allocated as follows:

6845 CRT controller: &FE00 to & FE01
In BASIC, this is accessed by the VDU 23 command. For example, VDU 23; R, V: 0; 0; 0 places the value V into register R of the CRT controller.

6845 ASIA: &FE08 to &FE09
This is where the parallel/serial conversion is carried out when accessing the cassette tape or the RS423.

Serial ULA: &FE10
ULA stands for 'Uncommitted Logic Array' which would imply it can be used for anything! It is one of the new breed of 'miracle' chips, containing the groundwork necessary to build a logic system of any desired form. In the initial stages of manufacture, it is rightly named an uncommitted logic array. However, before it leaves the factory the customer supplies further information which turns the previously uncommitted array into a conglomerate of committed functions. Thus, although the name ULA sticks, those in the BBC machine are certainly committed arrays. This particular ULA helps in the organisation of serial peripheral devices.

Video ULA : &FE20 to &FE21
The logic buried in this chip is responsible for much of the superb graphic and colour facilities available.

Paged ROM controller : &FE30
This is a simple decoder chip (74LS161) used to switch over the paged ROMs referred to earlier.

The internal VIA : &FE40 to &FE4F
There are two 6522 VIAs in the machine. This one is designated 'internal' because it is used for several purposes, indirectly concerned with the control of input and output.

The external VIA : &FE60 to &FE6F
This 6522 is dedicated to the parallel printer interface (Centronics) and the user port. The 6522 VIA consists of two, almost identical, halves. The 'A' side is committed to the printer and the 'B' side to the user port. As can be seen from the address range, the 6522 requires sixteen machine addresses in order to make full use of it. One function carried out on the 'A' side is the interrupt-driven clock used in the TIME keyword when in BASIC. The timers on the 'B' side are available for users' programs.

The floppy disk controller : &FE80 to &FE84
This is the home of the 8271 chip mentioned earlier.

Data link controller: &FEA0 to &FEA3
This is an advanced chip containing much of the logic required to control the Econet communications interface. It is part of the optional extras offered.

Analogue to digital converter : &FEC0 to &FEC2
This is the D7002 chip previously discussed.

At this point, it is worth repeating the earlier warning regarding the dangers of directly addressing any of these machine locations. However, the warning was in the nature of advice rather than a rule. There is nothing illegal in direct accessing the peripheral devices although, apart from the user port, it is unlikely that you will ever find the need to circumvent the resident operating system subroutines. The above information and addresses were primarily intended as background information. However, there will always be a few of the more intrepid readers who may feel a desire to 'improve' on the operating system, even at the risk of crashing or jeopardising the smooth running of a future second-processor.

Fred addresses and the 1 MHz Bus

Sheila addresses are concerned with what may be broadly described as standard peripherals. The BBC machine, however, caters for more ambitious schemes, such as Teletext, Prestel, dealer's test kits, etc. There is a multipin socket beneath the machine known as the 'I MHz Bus' which caters for these optional additions to the system. These are allotted addresses in the band &FC00 to &FCFF. This band (page &FC) is named Fred, a less charming name than Sheila but still quite novel. The individual allocations within Fred are as follows:

Dealer's test equipment: &FC00 to &FC0F
Testing and fault diagnosis of the BBC machine is rendered easier for dealers by a special box of tricks known as PET (no connection with Commodore's famous family of micros). PET stands for Progressive Establishment Tester and occupies sixteen locations within Fred's band.

Teletext : &FC10 to &FC13
Most readers will know that a Teletext adapter can be bought, enabling a range of free software to be down-loaded directly into the RAM locations from BBC transmissions. It is also possible to call up and incorporate any of the standard Teletext pages in your own programs. An updated list of the software available currently appears on page 701 of Teletext.

Prestel : &FC14 to &FC1F
Prestel is the Rolls Royce version of Teletext, providing access to an enormous, and still growing, storehouse of information. The information comes via the normal telephone system so it requires a rnodem (modulator and demodulator). A modem provides the necessary conversion from computer logic signals to audio tones, suitable for passing down a telephone line. The coupling is acoustical, rather than wired, in order to circumvent the rules relating to unauthorised interference with telephone equipment. Prestel is two-way in action, meaning you can also send your own messages back to Prestel. There is one snag of course - you have to pay for telephone calls and also an extra charge on top for certain of the Prestel pages.

Test equipment : &FC80 to &FC8F
Some more allocations for testing purposes.

Reserved for user's applications : &FCC0 to &FCFE
There is an ever-growing range of hardware available designed to plug into the 1 MHz bus. As can be seen from above, a generous range of addresses are left vacant for the purpose, sixty-three in fact.

ROM paging register : &FCFF
This is a single byte address used for paging different ROMs. (See JIM address band.)

JIM addresses and the 1 MHz bus

The address band &FD00 to &FDFF is called JIM and is primarily designed for connecting up alternative memory chips (up to 64K of RAM or ROM) via the I MHz bus. Note that the word 'alternative' is used rather than 'extra' because the full 64 K can only be page-accessed in competition with the resident 64K. Connecting up the memory is not a task you should attempt unless you feel confident or, preferably, have gained some experience with decoding logic (some general information on logic can be found in Appendix A). In the meantime, it is worth mentioning that the solitary address &FCFF, called the 'paging register' in the Fred band, will be found to have important significance to the decoding network.

Wiring details of the 1 MHz bus

Page 503 of the User Guide gives a diagram of the connections to the 1 MHz bus. However, a scaled down version is shown in Fig. 1.4 which tends to emphasise the decoding problem.
There are several abbreviations in the diagram which may demand translation. One of the more depressing features of computer hardware is the proliferation of abbreviations which designers use. T o the designer, the letter groups may be 'plain English' because of familiarisation. To the non-expert, they present a fearsome obstacle to progress, made worse by the lack of standardisation.
The 1 MHz socket pins are labelled the same as on page 503 of the User Guide but make no attempt to show the correct orientation of the corresponding pin numbers. You must refer to the original diagram in the User Guide if you intend to use the bus. The position of the 6502 microprocessor has been included in order to gain an overall perspective of the bus. Discussion of the wiring can be treated under three headings, the address bus, the data bus, and finally the control lines.

Figure 1.4. Simplified drawing of the 1 MHz bus.

The address bus

There are 16 wires on the address bus of the 6502 microprocessor, labelled A0 to A15. Only the 8 lower order wires, however, A0 to A7 are brought out to the I MHz bus. In order to provide the bus with high current drive, a 74LS244 non-inverting buffer (IC71) is used. The chip has no logic function but the wires are electrically stronger when they emerge. The address bus is one-way only. That is to say, signals can only pass from the microprocessor.

The data bus

The 8 wires, D0 to D7, from the microprocessor pass the 1 MHz bus via a two-way non-inverting buffer (IC72). This is a 74LS245, a more complicated buffer than the one used on the address bus because it must allow signals to pass to and from the microprocessor. Obviously, it cannot pass signals both ways at once so it must be controlled to either READ (pass data to the microprocessor) or WRITE (pass data from the microprocessor). The control terminal on the chip is labelled T/R which means 'Transmit/Receive'. Why wasn't it labelled R/W to make it tie up with READ and WRITE? The answer is due to the general purpose nature of logic chip design. A bidirectional buffer could have many uses apart from reading and writing to and from memory so it uses the wider terms 'transmit/receive'. Another control on the buffer is labelled CE which stands for 'Chip Enable'. This allows the entire chip to be switched ON/OFF or, using established jargon, enabled or disabled. Thus, the buffer can be placed in any one of three states, the READ state, the WRITE state or completely OFF altogether. When in the OFF state, the microprocessor data bus is completely unaware of its existence. It is said to be 'floating'.

The control lines

The address and data buses are well-defined entities. By comparison, the control fines of any computer system always seem an unruly mess. Odd-looking single lines carrying funny labels appear to wander around different parts of the microcomputer in an undisciplined manner. The sheer complexity of the complete microcomputer wiring means that only parts of it can be shown at once. This means that some of the control fines appear to end abruptly, only to appear again on another diagram, apparently starting from nowhere! To assist bewilderment, some of the address wires may be used to 'control' and data wires may even be used for addressing purposes. There are no short-cuts to understanding, it's merely a case of methodical plodding through each control and gradually becoming accustomed to the strange-looking abbreviations. Referring to Fig. 1.4 again and dealing with the easier parts first:

The power lines
The bus supplies a +5V and a 0V line for your external use although it is not to be treated as an inexhaustible source of power. However, it should be ample for running extra memory and/or a reasonable collection of logic chips.

Reset fine (labelled NRST)
It is important that all parts of the computer and any equipment you may add on to the I M Hz bus begin in step with each other. The microprocessor sends out a master reset signal which, in 6502 data sheets, is labelled RST. The bar over the top is a well-standardised method of indicating reverse logic, the bar standing for the word 'not', indicating that reset action will occur on a logic 0 rather than a logic 1 (for further details on logic, see Appendix A). For some obscure reason, the 1 MHz bus uses the prefix 'N' instead of the bar, to indicate reverse logic. So the line which starts off from the microprocessor as RST, emerges out of the bus as NRST (the N meaning 'not').

Read/write control (labelled R/NW)
The 6502 microprocessor labels the line R/W. This indicates that a logic 1 on the fine cause a READ and a logic 0 causes a WRITE. Note it is used to control the T/R terminal of the two-way buffer as well as providing an external line to the 1 MHz bus.

The 1 MHz clock (labelled 1 MHzE)
The source of the oscillator, known as the 'clock', is not shown. It may be required for external projects which require timing synchronisation with the resident clock system. It is worth mentioning at this point that the resident 'master clock' is 2 MHz, so external projects run at half speed. This is not a bad thing because the lower the frequency, the less critical you need be on the choice of components.

Analogue in
This allows an additional signal to be picked up and fed to the audio circuits of the computer, Any signal here is superimposed on any other audio signals. It is not an extra channel. The rms signal voltage must not exceed 3 millivolts or distortion and possibly damage may occur.

Interrupt request (labelled NIRQ)
This caters for external projects which rely on interrupt procedures, such as an extra 6522 VIA, or perhaps the more simple 6520 PIA. It enters the microprocessor under the label IRQ which means Interrupt ReQuest. As the bar over the top shows, it recognises only a logic 0. Although not shown on the diagram, there are several other contenders for interrupt. Because there is only a single line available, the various interrupt inputs are normally wire-ored (see Appendix A).

Non-maskable interrupt (labelled as NNMI)
This is brought out for external use but using it is fraught with danger of a crash. A signal on this line could endanger the operating system which expects to have exclusive rights to it. You are strongly advised to forget that it even exists!

Fred and JIM (labelled as NPGFC and NPGFD respectively)
NPGFD stands for Not PaGE FD, indicating that it is logic 0 active. Earlier discussions on FRED and JIM described them as particular pages (&FC and &FD) in memory. It now seems odd that single wires should have similar names. The answer is that the data lines D0 to D7 on the 1 MHz bus must only be activated when either of these pages are addressed - that is to say, only when the higher order pair of the hex digit addresses are FC or FD. Figure 1.4 gives no indication of the source of the FRED and JIM wires, but it is evident that they must somehow be fed from a decoder which senses when the higher order address lines (A8 to A15) carry the binary code corresponding to &FC or &FD. Full technical drawings of the BBC machine are difficult to obtain, so Fig. 1.5 is offered as one way the decoding might have been arranged.

Fig. 1.5. Decoder for producing Fred and Jim.

The decoding uses NAND gates which deliver a logic 0 only when all inputs are at logic I. The binary pattern for &FC is 1111 1100 so two logic inverters are necessary from fines A8 and A9. The binary pattern for &FD is 1111 1101 so only one logic inverter is required from address line A9.
Referring back to Fig. 1.4, the Jim and Fred lines are fed, via two diodes, to the chip enable (CE) pin on the two-way data buffer. Note that this pin has a tiny 'bubble' at the input which is a standard symbol indicating that reverse logic is required. (This explains why a NAND instead of an AND gate was used in Fig. 1.5.) Thus, the data bus is only routed to the I MHz bus when the chip is enabled by prior selection of Fred or Jim.
A few words of explanation may be needed with regard to the two diodes. In conjunction with the 3.3K resistor (R108), they form an OR gate for reverse logic. The register normally pulls CE high to +5 V, disabling the buffer chip. When a logic 0 from either Fred or Jim appears at the cathodes, the appropriate diode conducts and pulls the CE pin down towards 0 volts which enables it.

Suggestions for 1 MHz bus projects

The previous explanation of the bus will be interesting only to those who use, or have a yearning to construct their own extension systems. It is surprising how newcomers to machine code often become more interested in hardware projects even if they have previously showed little curiosity. This is because machine code programming probably creates more interest in computing theory and logic systems than BASIC or most high level languages. The I M Hz bus is beautifully designed for expanding the capabilities of the machine and experimenting. It would be a shame if your socket is always left vacant and collecting dust. Assuming you have never before tackled logic design or construction, the following advice may get you started:

  1. Obtain a copy of Application Note 1: The 1 MHz Bus from Acorn. This gives a well detailed description of the bus although you may find it a little heavy-going in parts.
  2. Scan through magazines which cater for both hardware and software. Electronics and Computing is a good example, and it is usually refreshingly free from articles by games fanatics.
  3. Study Appendix A of this book and supplement it with one of the many books available on logic theory. Jan Sinclair's Beginner's Guide to Digital Electronics is excellent
  4. Get a friend, or become friendly with someone, who is knowledgeable in the field of electronics. There are usually one or two of these types lurking around your local computer club. However clever you become at logic design, you may require some expertise in electrical matters, if only to avoid damage to the equipment. Soldering plugs, sockets and 1C pins is not quite the simple exercise we are sometimes led to believe.

Almost any device can be switched ON or OFF by computer instructions providing it is controlled by a logic 1 or a logic 0. The device can be a simple lamp, the jib or winding gear of a crane, the points on a model railway or even one of the many chips available in the '74' series described in Appendix A. From now on, it will be assumed that the term 'device' is logic controlled so it is unnecessary to burden the mind with its particular function.

Address decoding

If there are several different devices, each one must have an associated code acting as an identifier. This code will be the device 'address'. The 1 MHz bus is equipped with address wires A0 to A7 which can be tapped for supplying the two least significant hex digits of the address. The two most significant hex digits have already been decided for us since the I M Hz bus is restricted to page FC for device control. As explained previously, the line marked NPGFC is available on the bus to enforce this page. There are 256 different address codes possible on one page according to the binary pattern set up on A0 to A7. That is to say, the address range of our page FC extends in theory from &FC00 to &FCFF. However, we should restrict the coding of our special devices to the small band set aside for User Applications, &FCC0 to &FCFE. It is comforting to know that decoding A0 to A7 is easily achieved by special decoder chips available in the 74 series. These decoders are general purpose but skilfully designed for slipping neatly into a variety of systems. Figure 1.6 shows a possible hook up for driving any one of eight devices.

Fig. 1.6. Selecting any one of eight devices.

The 74LS138 is a well-known decoder chip. It has eight individual output lines, only one of which can be 'activated' at any one times The output chosen to be active depends on the binary pattern applied to the three select lines. However, whatever the select pattern applied, the chip will still not be functional until all three enable lines are correctly driven. The combination of selection and enabling can be used to provide unique address decoding for each of the outputs. Working out address decoding is an art which is essential for those who intend to design their own add-on boards, so the following step-by-step explanation of Fig. 1.6 is worth studying carefully. The explanation is limited to one of the outputs (pin 15) labelled as address FCF0:

Thus, to switch ON any device connected to pin 15 of the decoder chip, all we have to do is to specify address &FCF0.
If all this appears difficult, it may help if you-pencilled in the binary pattern for F0 on the eight address lines as follows:

A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 0 0

Tracing the '1's and '0's back to the decoding chip will confirm that the chip is fully enabled (with pin 15 activated) only by the address &FCF0.
What about the other seven outputs? The only difference will be the pattern on the three select fines driven from A0, A1 and A2. The internal design of the decoder chip ensures the following behaviour:

A2 A1 A0 Output selected (hex address)
0 0 0 pin 15 FCF0
0 0 1 pin 14 FC1F
0 1 0 pin 13 FCF2
0 1 1 pin 12 FCF3
1 0 0 pin 11 FC1F
1 0 1 pin 10 FCF5
1 1 0 pin 9 FCF6
1 1 1 pin 7 FCF7

Although Fig. 1.6 has been built around the addresses &FCF0 to &FCF7, we could have chosen any other set of eight contiguous addresses in Fred's user application band (&FCC0 to &FCFE). For example, suppose for some reason we wished to position the decoder in the eight addresses &FCE0 to &FCE7. The third hex digit would now be E (binary 1110) instead of F (binary 1111). The only change, therefore, would be a logic 0 on address line A4 instead of a logic 1. Thus the circuit remains the same except for one extra inverter in between A4 and the NAND gate.
Note from Fig. 1.6 that the data bus is not involved. Switching on the selected advice is simply a case of mentioning the address in a machine code instruction; any data transfers by READ or WRITE action are incidental to device action. We could say that the device is 'address' rather than 'data' driven.

Sending parallel data externally

Some devices only require a single logic line to activate them (simple lamp or electric motor). Others, may require a number of data lines as, for example, an 8-bit digital to analogue converter. Driving such devices would involve the data bus as well as the address bus. As far as address decoding is concerned, we could enable the device from any one of the outputs in Fig. 1.6 or, in fact, up to eight separate ones if the necessity arises. Figure 1.7 shows how the device-select action is combined with the data bus.

Fig. 1.7. An 8-bit latch as an example of a device.

An 8-bit latch is a kind of buffer between the data source (in this case the data bus) and the device which requires it. The device only accepts the data when a terminal called the clock changes state. Because the clock input in Fig. 1.7 has a bubble, clocking the data takes place when the change is from logic I to logic 0. In the quiescent state (device not yet selected) the parallel data out is that which remained from the last time the latch was clocked: it is 'historic' data. However, whenever &FCF0 is addressed (goes from logic 0 to logic 1), the inverter in the line causes the clock to go from logic 1 to logic 0. The information on the data bus then passes through to the parallel output lines. To summarise: when &FCF0 is addressed, the device immediately receives new information from the data bus, overwriting the previous information. As a matter of interest, the machine code line to place the contents of the accumulator into the output lines is:

STA &FCF0

The system recognises the instruction is to act on the 1 MHz bus devices because the first two hex digits of the address is the Fred page.

Fig. 1.8. Converting digital information to analogue

Figure 1.8 is another example of a device requiring the data bus, which is needed, of course, for receiving the digital data.
Although the BBC machine is not equipped with a digital to analogue converter, it is easy to hook one on the 1 MHz bus. There are several types available so the diagram contains only sufficient detail for the understanding of the system. The diagram shows the data bus directly connected to the D/A converter and enabled by one of the decoded addresses. This, of course, could be one of the lines from a 74LS138 (as shown earlier in Fig. 1.6). An instruction to produce analogue output could be:

STA &FCF2

This will cause the output voltage to assume a value proportional to the digital number in the accumulator.

Using the R/NW line

Up to this point, the devices described have all delivered outputs, from the computer to the outside world. However, many systems may include one or more input devices passing data from the outside world to the computer. One obvious example is an analogue to digital converter. There are two dangers inherent in the design of input devices. The first is obvious: make sure that the voltages coming from the outside world are within the allowed maximum (usually within the range 0 V to 5 V). The second danger is more obscure. If an input device is enabled, it normally places data on the address bus. Thus the instruction should READ from the data bus (an LDA for example). But if, by mistake, we WRITE (an ST A, for example) there is a conflict of loyalties on the data bus because two independent sets of data are trying to gain control, This could damage some of the circuits. The remedy is either to become an infallible programmer (we have never yet met one) or incorporate something on the lines shown in Fig. 1.9.
In Fig. 1.9, a NAND gate is fed by the R/NW line and the decoded device address. The output from the gate is logic 0 only if both inputs are logic 1. Therefore, even if the device address is correct (FCF4 in the example) the R{NW fine must be logic 1 which is present only if the instruction is to READ. If, in error, the programmer causes a WRITE action, the R/NW line is turned to logic 0 and the N AND output rises to logic I. Because the device in Fig. 1.9 has a bubble at the enable input, the input device is not enabled. Thus, it is now impossible to jam the data bus by trying to write to an input device. If the device had no enable bubble (and some of them haven't), it would be necessary to include an inverter in the N AND output fine. This latter point illustrates how easy it is to be 'one inversion out' when designing logic systems. Y on can never be just a little bit out (as in analogue design). It is either dead right or dead wrong!

Figure 1.9. Gating the READ/WRITE line to input devices

Using Jim to access auxiliary memory

Fred is used for attaching a variety of extra gadgets to the 1 MHz bus. Jim is virtually dedicated to the sole purpose of adding on auxiliary blocks of memory. Up to the full 64K of RAM, ROM or mixtures of RAM and ROM can be page accessed. For full details, it is advisable to obtain the Acorn leaflet on the 1 MHz bus but, in the meantime, Fig. 1.10 shows the general idea.
As mentioned previously, a sixteen-wire bus is required to cover a 64K memory system. Only eight-address wires, A0 to A7, are provided on the 1 MHz bus so it is not surprising that the solution to such a problem involves some strange goings-on. Examining Fig. 1.10 reveals that the lower order addresses are supplied by the legitimate address bus. The higher order address, A8 to A15 is obtained by 'borrowing' the data bus. How can the data bus (which is required to pass data to an address) simultaneously supply part of the address as well? The simple answer is that it can't. The secret lies in the 8-bit latch. The programmer first supplies the higher order address (the page). This is then automatically clocked into the latch, supplying A8 to Al5 in the ROM/RAM. The figure shows that latch clocking is achieved by the special decoded line FCFF. It also shows that the entire ROM/RAM memory structure is only enabled by using the Jim address band, detected by the NPGFD line on the 1 MHz bus. Although the enabling pin is marked 'valid memory address' (instead of 'enable'), the effect is identical.
There is naturally a small penalty to pay for all this jiggery pokery. It takes a little longer to read or write to a location in the extended memory, particularly if the desired address is outside the current page (outside the 'page boundary'). Some provisional details of the coding are now given in the hope of clarifying some of these points:

Programming procedure:

Example: to store the number 13 hex in address &3567 of the extended memory.

LDA #&13 \load A with &13
LDX #&35
STX &FCFF \store page address in paging register
STA &FD67 \store A in address &67 of page &35

The paging register location, &FCFF is the odd man out in the Fred band because it is used for Jim.
It is unnecessary to keep loading the paging register each time, providing the addresses lie on the same page. If the next address lies on a different page, then the paging register must be reloaded.

Summary

  1. Machine code programming can be tackled with more confidence if backed by some knowledge of hardware.
  2. If your machine still has the old 0.1 series ROM, get it changed to the 1.2 or any of the 1.X series as soon as possible.
  3. The priority on power-up is vested in the ROM occupying the rightmost of the five sockets.
  4. The designer's advice is to access the peripheral interfaces by resident subroutines, OSBYTE, OSWORD, etc. This is good advice but need not be taken too seriously during the learning stage of machine code programming.
  5. The operating system handles standard peripherals by a process of orderly interrupts6. An interrupt request (IRQ) is granted only if the mask bit (in the microprocessor) has not been set to '1'. A non-maskable interrupt, or NMI ignores the mask bit.
  6. Parallel interfaces transmit or receive a complete byte at a time, requiring 8 wires to carry the information. Serial interfaces pass only single bits, one after the other, on a single line.
  7. The RS423 (an improved version of the older RS232) is a serial interface which can handle certain printers, telephone signals via a modem or act as a data link between other computers.
  8. A 6850 chip handles serial and a 6522 chip handles parallel interfacing.
  9. The A/D conversion chip, a D7002, allows any one of four varying (analogue) input voltages to be represented as a digital number.
  10. The heart of the floppy disk interface is the 8271 controller chip.
  11. Memory maps divide the 64K total into 64 pages. A machine address is a four-hex-digit number. The left-hand pair is the page and the right-hand pair the address on the page.
  12. One page of memory contains 256 addressable locations (this is exactly 100 in hex notation).
  13. Sheila is page FE, occupying the address band &FE00to &FEFF. It is reserved for accessing all interfaces built into the machine.
  14. Fred is page FC, occupying the address range &FC00 to &FCFF. It is reserved for any specialised hardware fed from the 1 MHz bus, such as dealer's test equipment, Teletext, Prestei, etc.
  15. A small area of the Fred page is reserved for the user's special applications, &FCC0 to &FCFE.
  16. The 1 MHz bus (see Fig. 1.4) provides eight address lines, A0 to A7 and eight data wires via a two-way buffer (IC72). A 5 volt power supply and special lines are also provided.
  17. The special lines on the 1 MHz bus include:
    NNMI and NIRQ provide interrupt inputs to the microprocessor. They are activated by logic 0.
    NRST delivers logic 1 during a READ instruction and logic() during a WRITE.
    NRST delivers a logic 0 when reset is activated.
    NPGFC delivers a logic 0 whenever page FC (Fred) is addressed.
    NPGFD delivers logic 0 whenever page FD (Jim) is addressed. (The data buffer is only enabled if either Jim or Fred pages are addressed. The 1 MHz clock is an oscillator, sychronised to the 2 MHz microprocessor clock but running at half the frequency. Analogue-in is connected to the sound channels. Any signal supplied is added to any other programmed sound. It is not a separate channel.
  18. Detailed information on the 1 MHz bus can be obtained from Acorn corn puters.
  19. Jim is the FD page, occupying the address range &FD00to &FDFF. It caters for a 64 K memory expansion.
  20. Some devices require only a simple ON/OFF drive obtained by a simple decoder from the address bus. The data bus is not required.
  21. A 74LS138 is a useful decoding chip, capable of activating any one of eight devices. The address for each device is determined by the '1's and '0's applied to the select and enabling inputs.
  22. Devices which deliver data from the outside world (input devices) should be gated with the read} write line (R{NW) in case a WRITE instruction is given in error (see Fig. 1.9).

Self test

  1. If a ROM or EPROM is 'empty', what hex number appears when you read any location?
  2. You might expect a parallel printer interface to be eight times quicker than a serial. Why is there virtually no difference?
  3. State an advantage of the RS423 serial interface over the earlier RS232.
  4. Name a device which could convert, say, atmospheric pressure readings to a proportional voltage.
  5. What approximate voltage gives full-scale reading at the analogue/ digital input?
  6. What is the highest hex page number?
  7. What specialised names are given to pages FC, FD and FE?
  8. The user port and the Centronics printer interface are fed by a 6522 VIA. On which side of the VIA is the user port?
  9. How would you find out which version of ROM operating system is installed?
  10. Which instruction in the 6502 will prevent IRQ being granted?
  11. Passing an ASCII character via the RS423 interface requires ten bits. Why?
  12. What is the approximate voltage across a silicon diode when in forward conduction?
  13. With reference to Fig. 1.6, what address would activate pin 12 if the inverter to pin 6 was omitted in error?
  14. With reference to Fig. 1.8, if the maximum output is 2.55 volts, what output voltage is obtained when the digital data is 3F hex?
  15. With reference to Fig. 1.7, assume the data bus is 4F hex and the latch output is also 4F. Supposing the data bus now changes to 5F, what is the output from the latch prior to the arrival of the clock pulse?
  16. With reference to Fig. 1.4 some pins on the 6502 have a bar across the label. What is the significance?
  17. Some logic chips have a pin labelled CE. What does this mean?
  18. The address band within F red allotted to User Applications is &FCC0 to &FCFE. How many different addresses are within this band?
  19. The last address in the Fred band is &FCFF. What is significant about this special address?
  20. Sheila addresses are reserved for . . . ?
  21. Jim addresses are reserved for . . . ?
  22. Fred addresses are reserved for . . . ?

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