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Answers to Self Test Questions
Chapter One
FF.
Because the delay caused by the electronics, even when using serial transmission, is negligible in relation to the printer mechanics.
The transmission cable can be much longer.
General term is 'transducer'.
1.8 volts.
FF.
FC=FRED. FD=JIM. FE=SHEILA.
The 'B' side.
Key *HELP.
SEL
8 for ASCII and 2 for START/STOP.
0.6 volts.
Any address within the range FC03 to FCE3.
0.63 volts.
Same as before, 4F. It doesn't change until the next clock pulse arrives.
The bar negates the logic. For example, NOT A can be written as A.
Chip enable.
63.
FCFF is the paging register in the FRED band, used for supplying the JIM page address.
Resident peripheral interfaces.
The 1 MHz bus.
Primarily reserved for extra ROM/RAM.
Chapter Two
Dynamic (DRAMs).
Expensive and lower packing density.
Each peripheral is activated by a specific address (or addresses), other than by a special op-code.
By special op-code in the instruction set.
It supports the true arithmetical operations, addition and subtraction. Many of the instructions only perform on the accumulator.
&2D03.
Each bit is an independent flag.
D,I and C.
D,I.
N, V ,B and Z.
When working in unsigned binary.
It is activated by bit 6 of the data during the BIT test.
The last instruction left non-zero data.
The C bit
Page I or RAM.
Via the X register, using TXS.
Before.
C.
High-byte.
The program counter.
The next higher address.
R/W (sometimes written R/NW).
Fixed by the microprocessor designers.
The Instruction Register, IR.
If by software BRK, the B bit is set in the status register.
The 8080.
Chapter Three
STA memory.
ASL A.
ADC memory.
AND #&DF.
EOR #&48.
ORA #&04.
&EE.
Double-byte operand not allowed in immediate addressing.
Program counter.
112 to 143 inclusive.
&11.
JMP.
X register.
Indirect indexed.
&74.
&79.
Post-indexed indirect.
Chapter Four
Full-stop between BNE and Label is wrong.
OPT.
3.
No, because &83 is a negative relative address.
(a) 02 (b) 04 (c) 05.
(a) 56 (b) 12.
PRINT ~!34587.
Chapter Five
0000 0011.
0000 1001.
&FF.
2000 million.
No.
Chapter Six
Wordlength, clock frequency, instruction repertoire, operating system and language interpreter.
No formal answers are applicable to tests 6.2 to 6.5, 7.1 to 7.5 and 8.1 to 8.4.
Chapter Nine
&FE6D.
&FE69.
&DF.
CB1.
Bit 4 and bit 7 in the IER must be set and the I-bit in the process status register must be reset.
Set bit 1 in the ACR.
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