ADC | Add with carry | A+M+C®A | NZCV |
Address mode | Op-code | Bytes | Cycles |
Immediate | &69 | 2 | 2 |
Zero-page | &65 | 2 | 2 |
Zero-page,X | &75 | 2 | 4 |
Absolute | &6D | 3 | 4 |
Absolute,X | &7D | 3 | 4 or 5 |
Absolute,Y | &79 | 3 | 4 or 5 |
(Indirect,X) | &61 | 2 | 6 |
(Indirect),Y | &71 | 2 | 5 |
AND | And with A | A and M®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &29 | 2 | 2 |
Zero-page | &25 | 2 | 2 |
Zero-page,X | &35 | 2 | 4 |
Absolute | &2D | 3 | 4 |
Absolute,X | &3D | 3 | 4 or 5 |
Absolute,Y | &39 | 3 | 4 or 5 |
(Indirect,X) | &21 | 2 | 6 |
(Indirect),Y | &31 | 2 | 5 |
ASL | Shift left | C¬(7...0)¬0 | NZC |
Address mode | Op-code | Bytes | Cycles |
Accumulator | &0A | 1 | 2 |
Zero-page | &06 | 2 | 2 |
Zero-page,X | &16 | 2 | 6 |
Absolute | &0E | 3 | 6 |
Absolute,X | &1E | 3 | 7 |
BCC | Branch if C=0 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &90 | 2 | 3 or 2 |
BCS | Branch if C=1 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &B0 | 2 | 3 or 2 |
BEQ | Branch if Z=1 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &F0 | 2 | 3 or 2 |
BIT | A and M, M7®M,M6®V | Z,N,V | |
Address mode | Op-code | Bytes | Cycles |
Zero-page | & | 2 | 2 |
Absolute | & | 3 | 4 |
BMI | Branch if N=1 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &30 | 2 | 3 or 2 |
BNE | Branch if Z=0 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &D0 | 2 | 3 or 2 |
BPL | Branch if N=0 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &10 | 2 | 3 or 2 |
BRK | Break | PC+2 | I flag=1 |
Address mode | Op-code | Bytes | Cycles |
Implied | &00 | 1 | 7 |
BVC | Branch if V=0 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &50 | 2 | 3 or 2 |
BVS | Branch if V=1 | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Relative | &70 | 2 | 3 or 2 |
CLC | Clear Carry | C flag = 0 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &18 | 1 | 2 |
CLD | Clear Decimal | D flag=0 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &D8 | 1 | 2 |
CLI | Clear I mask | I flag=0 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &58 | 1 | 2 |
CLV | Clear overflow | V flag=0 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &B8 | 1 | 2 |
CMP | Compare A | A-M | NZC |
Address mode | Op-code | Bytes | Cycles |
Immediate | &C9 | 2 | 2 |
Zero-page | &C5 | 2 | 2 |
Zero-page,X | &D5 | 2 | 4 |
Absolute | &CD | 3 | 4 |
Absolute,X | &DD | 3 | 4 or 5 |
Absolute,Y | &D9 | 3 | 4 or 5 |
(Indirect,X) | &C1 | 2 | 6 |
(Indirect),Y | &D1 | 2 | 5 or 6 |
CPX | Compare X | X-M | NZC |
Address mode | Op-code | Bytes | Cycles |
Immediate | &E0 | 2 | 2 |
Zero-page | &E4 | 2 | 3 |
Absolute | &EC | 3 | 4 |
DEC | Decrement M | M-1®M | NZ |
Address mode | Op-code | Bytes | Cycles |
Zero-page | &C6 | 2 | 5 |
Zero-page,X | &D6 | 2 | 6 |
Absolute | &CE | 3 | 6 |
Absolute,X | &DE | 3 | 7 |
DEX | Decrement X | X-1®X | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &CA | 1 | 2 |
DEY | Decrement Y | Y-1®Y | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &88 | 1 | 2 |
EOR | Exclusive OR | AexcM®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &49 | 2 | 2 |
Zero-page | &45 | 2 | 2 |
Zero-page,X | &55 | 2 | 4 |
Absolute | &4D | 3 | 4 |
Absolute,X | &5D | 3 | 4 or 5 |
Absolute,Y | &59 | 3 | 4 or 5 |
(Indirect,X) | &41 | 2 | 6 |
(Indirect),Y | &51 | 2 | 5 |
INC | Increment M | M+1®M | NZ |
Address mode | Op-code | Bytes | Cycles |
Zero-page | &E6 | 2 | 5 |
Zero-page,X | &F6 | 2 | 6 |
Absolute | &EE | 3 | 6 |
Absolute,X | &FF | 3 | 7 |
INX | Increment X | X+1®X | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &E8 | 1 | 2 |
INY | Increment Y | Y+1®Y | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &C8 | 1 | 2 |
JMP | Jump | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Absolute | &4C | 3 | 3 |
Indirect | &6C | 3 | 5 |
JSR | Jump | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Absolute | &20 | 3 | 3 |
LDA | Load A | M®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &A9 | 2 | 2 |
Zero-page | &A5 | 2 | 3 |
Zero-page,X | &B5 | 2 | 4 |
Absolute | &AD | 3 | 4 |
Absolute,X | &BD | 3 | 4 or 5 |
Absolute,Y | &B9 | 3 | 4 or 5 |
(Indirect,X) | &A1 | 2 | 6 |
(Indirect),Y | &B1 | 2 | 5 or 6 |
LDX | Load X | M®X | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &A9 | 2 | 2 |
Zero-page | &A5 | 2 | 3 |
Zero-page,Y | &B5 | 2 | 4 |
Absolute | &AD | 3 | 4 |
Absolute,Y | &B9 | 3 | 4 or 5 |
LDY | Load Y | M®Y | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &A0 | 2 | 2 |
Zero-page | &A4 | 2 | 3 |
Zero-page,Y | &B4 | 2 | 4 |
Absolute | &AC | 3 | 4 |
Absolute,Y | &BC | 3 | 4 or 5 |
LSR | Logical SR | 0®(7...0)®C | N=0,ZC |
Address mode | Op-code | Bytes | Cycles |
Accumulator | &4A | 1 | 2 |
Zero-page | &46 | 2 | 2 |
Zero-page,X | &56 | 2 | 6 |
Absolute | &4E | 3 | 6 |
Absolute,X | &5E | 3 | 7 |
NOP | No operation | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Implied | &EA | 1 | 2 |
ORA | Inclusive OR | A or M®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Immediate | &09 | 2 | 2 |
Zero-page | &05 | 2 | 2 |
Zero-page,X | &15 | 2 | 4 |
Absolute | &0D | 3 | 4 |
Absolute,X | &1D | 3 | 4 or 5 |
Absolute,Y | &19 | 3 | 4 or 5 |
(Indirect,X) | &01 | 2 | 6 |
(Indirect),Y | &11 | 2 | 5 |
PHA | Push A | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Implied | &48 | 1 | 3 |
PHP | Push status | Flags unaltered | |
Address mode | Op-code | Bytes | Cycles |
Implied | &08 | 1 | 3 |
PLA | Pull A | NZ | |
Address mode | Op-code | Bytes | Cycles |
Implied | &68 | 1 | 4 |
PLP | Pull status | Flags as status | |
Address mode | Op-code | Bytes | Cycles |
Implied | &28 | 1 | 4 |
ROL | Rotate L | ¬(7...0)¬C¬ | NZC |
Address mode | Op-code | Bytes | Cycles |
Accumulator | &2A | 1 | 2 |
Zero-page | &26 | 2 | 2 |
Zero-page,X | &36 | 2 | 6 |
Absolute | &2E | 3 | 6 |
Absolute,X | &3E | 3 | 7 |
ROR | Rotate R | ®C®(7...0)® | NZC |
Address mode | Op-code | Bytes | Cycles |
Accumulator | &6A | 1 | 2 |
Zero-page | &66 | 2 | 2 |
Zero-page,X | &76 | 2 | 6 |
Absolute | &6E | 3 | 6 |
Absolute,X | &7E | 3 | 7 |
RTI | Return from I | Flags as pulled | |
Address mode | Op-code | Bytes | Cycles |
Implied | &40 | 1 | 6 |
RTS | Return from SR | Flags analtered | |
Address mode | Op-code | Bytes | Cycles |
Implied | &60 | 1 | 6 |
SBC | Subtract | A-M-C®A | NZCV |
Address mode | Op-code | Bytes | Cycles |
Immediate | &E9 | 2 | 2 |
Zero-page | &E5 | 2 | 2 |
Zero-page,X | &7F | 2 | 4 |
Absolute | &ED | 3 | 4 |
Absolute,X | &FD | 3 | 4 or 5 |
Absolute,Y | &F9 | 3 | 4 or 5 |
(Indirect,X) | &E1 | 2 | 6 |
(Indirect),Y | &F1 | 2 | 5 or 6 |
SEC | Set carry | C=1 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &38 | 1 | 2 |
SED | Set decimal | D=1 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &F8 | 1 | 2 |
SEI | Set I mask | I=1 | |
Address mode | Op-code | Bytes | Cycles |
Implied | &78 | 1 | 2 |
STA | Store A | A®M | Flags unaltered |
Address mode | Op-code | Bytes | Cycles |
Zero-page | &85 | 2 | 3 |
Zero-page,X | &95 | 2 | 4 |
Absolute | &8D | 3 | 4 |
Absolute,X | &9D | 3 | 5 |
Absolute,Y | &99 | 3 | 5 |
(Indirect,X) | &81 | 2 | 6 |
(Indirect),Y | &91 | 2 | 6 |
STX | Store X | X®M | Flags unaltered |
Address mode | Op-code | Bytes | Cycles |
Zero-page | &86 | 2 | 3 |
Zero-page,X | &96 | 2 | 4 |
Absolute | &8E | 3 | 4 |
STY | Store Y | Y®M | Flags unaltered |
Address mode | Op-code | Bytes | Cycles |
Zero-page | &84 | 2 | 3 |
Zero-page,X | &94 | 2 | 4 |
Absolute | &8C | 3 | 4 |
TAX | Transfer | A®X | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &AA | 1 | 2 |
TAY | Transfer | A®Y | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &A8 | 1 | 2 |
TYA | Transfer | Y®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &98 | 1 | 2 |
TSX | Transfer | SP®X | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &BA | 1 | 2 |
TXA | Transfer | X®A | NZ |
Address mode | Op-code | Bytes | Cycles |
Implied | &8A | 1 | 2 |
TXS | Transfer | X®SP | Flags unaltered |
Address mode | Op-code | Bytes | Cycles |
Implied | &9A | 1 | 2 |
Updates N, Z and C flags:
ADC,ASL,CMP,CPX,CPY,ROL,ROR,SBC.
Updates N and Z flags:
AND,DEC,DEX,DEY,EOR,lNC,INX,INY,LDA,
LDX,LDY,ORA,PLA,TAX,TAY,TYA,TSX,TXA.
Updates N, Z, C and V flags:
ADC,SBC.
Updates N, C and clears N:
LSR.
Op-codes not mentioned above either: (a) have no effect on processor flags
or
(b) set or reset certain flags by direct programming
(CLC,CLD,CLI,CLV,SEC,SED,SEI).
Immediate:
ADC,AND,CMP,CPX,CPY,EOR, LDA,LDX,LDY,ORA,SBC
Zero-page:
ADC,AND,ASL,BIT,CMP,CPX,CPY,DEC,EOR,INC,LDA,LDX,
LDY,LSR,ORA,ROL,ROR,SBC,STA,STX,STY
Zero-page,X
ADC,AND,AS L,CMP, DEC,EOR,IN C,LDA,LDY,LSR,ORA,ROL,
ROR,SBC,ST A,STY
Absolute:
ADC,AND,ASL,BIT,CMP,CPX,CPY,DEC,EOR,INC,JMP,JSR,
LDA, LDX,LDY,LSR,ORA, ROL,SBC,STA,STX,STY
Absolute,X:
ADC,AND,ASL,CMP,DEC,EOR,INC,LDA,LSR,ORA,ROL,ROR,
SBC,STA
Absolute,Y:
ADC,AND,CMP,EOR,LDA,LDX,ORA,SBC,STA
(Indirect,X):
ADC,AND,CMP,EOR,LDA,ORA,SBC,STA
(Indirect),Y:
ADC,AND,CMP,EOR,LDA,ORA,SBC,STA
Accutmulator:
ASL,LSR,ROL,ROR
Implied:
BRK,CLC,CLD.CLI,CLV,DEX,DEY INX,INY,NOT,PHA,PHP,PLA,
PLP,RTI,RTS,SEC,SED,SEI,TAX,TAY,TSX,TXA.TXS,TYA
Relative:
BCC,BCS,BEQ,BMI,BNE,BPL,BVC,BVS
The following instructions have no effect on status flags:
BCC,BCS,BEQ,BMI,BNE,BPL,BVC,BVS,JMP,JSR,NOP,PHA,PHP,
RTS,STA,STX,STY,TXS
In common use:
ADC BCC BCS BNE CLC CMP CPX CPY DEX DEY INX INY LDA LDX LDY RTS
SBC SEC STA STX STY TAX TAY TYA TXA
Often used:
BEQ ASL BMI BPL DEC INC JMP JSR LSR PLA PHA ROL ROR
Sometimes used:
AND BIT BRK BVC BVS CLV EOR NOP ORA
Seldom used:
CLD PHP PLP RTI SED SEI TSX TXS
The above classification must not be taken too seriously. It is very much a question of personal preference and programming style. It is doubtful if two writers would ever agree. However, it may still be useful, particularly if you are in the initial learning phaseabsolute address: the numerical number identifying an address. aceumulator: the main register within the microprocessor and the only one equipped for arithmetic.